1. Field of the Invention
The invention relates generally to conductor layers within microelectronic structures. More particularly, the invention relates to enhanced performance conductor layers within microelectronic structures.
2. Description of the Related Art
In addition to microelectronic devices, such as but not limited to transistors, resistors, capacitors and diodes, microelectronic structures, including in particular semiconductor structures, typically also include patterned conductor layers that are separated by dielectric layers. These patterned conductor layers are typically used for connecting and interconnecting the microelectronic devices within the microelectronic structures to form fully functional microelectronic circuits.
As microelectronic structure and device dimensions continue to decrease, and microelectronic structure and device performance expectations continue to increase, compromised performance of patterned conductor layer portions of microelectronic circuits are beginning to contribute commensurately greater proportions of overall compromised performance of microelectronic circuits. For example, patterned conductor layer based time delays are becoming an increasingly larger portion of overall semiconductor circuit based time delays when fabricating semiconductor circuits. In addition, as semiconductor structure and device dimensions decrease and patterned conductor layer dimensions also decrease, other detrimental patterned conductor layer effects, such as but not limited to electromigration effects, also become more prominent within microelectronic circuits.
Thus, desirable are semiconductor structures and methods for fabricating the semiconductor structures that include therein fully functional and reliable patterned conductor layers.